TSMC Paves Way for 5nm A14 Chip in 2020 iPhones

Paving the way for a 5nm-sized A14 chip in 2020 iPhones, TSMC has announced the release of its complete 5nm chip design infrastructure.


TSMC's continued packaging advancements coupled with Apple's industry-leading mobile chip designs is beneficial for the performance, battery life, and thermal management of future iPhones. That will continue with the 5nm process:
Compared with TSMC's 7nm process, its innovative scaling features deliver 1.8X logic density and 15% speed gain on an ARM® Cortex®-A72 core, along with superior SRAM and analog area reduction enabled by the process architecture. The 5nm process enjoys the benefits of process simplification provided by EUV lithography, and is making excellent progress in yield learning, achieving the best technology maturity at the same corresponding stage as compared to TSMC's previous nodes.
TSMC's 5nm process is already in preliminary risk production and the chipmaker plans to invest $25 billion towards volume production by 2020.

TSMC has been Apple's exclusive supplier of A-series chips since 2016, fulfilling all orders for the A10 Fusion chip in the iPhone 7 and iPhone 7 Plus, the A11 Bionic chip in the iPhone 8, iPhone 8 Plus, and iPhone X, and the A12 Bionic chip in the latest iPhone XS, iPhone XS Max, and iPhone XR.

TSMC's packaging offerings are widely considered to be superior to that of other chipmakers, including Samsung and Intel, so it's not surprising that its exclusivity is poised to continue with A13 chips in 2019 and A14 chips in 2020.

TSMC has been gradually shrinking the size of its dies over the years as it continues to refine its manufacturing process: the A10 Fusion is 16nm, the A11 Bionic is 10nm, and the A12 Bionic is 7nm. A13 chips will likely be 7nm+, benefitting from the process simplification of EUV lithography.


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TSMC on Course to Secure 5nm Chip Orders for 2020 iPhones

Apple chipmaker TSMC will miniaturize its fabrication process to 5 nanometers in a bid to secure orders for Apple's processors in its 2020 iPhones, according to industry sources cited in a DigiTimes report.


TSMC recently confirmed that it plans to invest $25 billion towards volume production of 5nm chips by 2020, and today's report backs expectations that those chips are likely headed for Apple's smartphones next year.
Despite its dim business and industry outlook this year, TSMC claimed it is making progress in the development of sub-7nm process technologies with plans to move a newer 5nm EUV process to volume production by 2020 well on track.
Previous successes in miniaturization have seen TSMC remain Apple's exclusive supplier of A-series chips for the last three years, beginning with the A10 Fusion chip in the iPhone 7/7 Plus, and continuing with the A11 Bionic chip in the iPhone 8/8 Plus and iPhone X, and the A12 Bionic in the iPhone XR/XS/XS Max.

The A10 Fusion chip is 16nm, the A11 Bionic is 10nm, and the A12 is a 7nm chip. The "A13" 5nm chip destined for this year's iPhones is also based on 7nm technology, but is expected to be the first chip to use extreme ultraviolet lithography (EUV), which allows for a more microscopic chip layering process.

The Taiwanese manufacturer has been gradually shrinking the size of its dies for several years now, allowing it to offer packages that are widely considered to be superior to that of other chipmakers, including Samsung and Intel.

End users can expect Apple's mobile chip designs and TSMC's continued packaging advancements to improve performance, battery life, and thermal management in future iPhones.

Tag: TSMC

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Apple Suppliers Cutting Sales Forecasts Amid ‘Extraordinary’ Decline in Chinese Demand

Major Apple suppliers in Asia have been cutting their 2019 sales forecasts and some have cited an "extraordinary" drop in Chinese demand, reports Nikkei.

Taiwan Semiconductor Manufacturing Co (TSMC), which supplies the A-series chips used in the iPhones and other devices, is forecasting a 22 percent drop in revenue for the January to March quarter. TSMC said there was a "sudden drop in demand" for high-end smartphones, also attributing its revenue decline to the U.S.-China trade war and economic uncertainty.


The same thing goes for Nidec, a company that supplies the vibration motor in the iPhone. Nidec has dropped its full-year profit outlook by upwards of 25 percent after slumps were seen in November and December.
"We have faced extraordinary changes," Nidec Chairman Shigenobu Nagamori told reporters at a Thursday news conference as the company reversed a previous forecast of a record profit. [...]

The tide shifted in November, however. "We saw big slumps in November and December," Nagamori said. "Orders, sales and shipments in all business segments around the world saw major shifts," he explained.
Apple has forecast its own decline in revenue, dropping guidance for the holiday quarter to $84 million, down from an earlier November estimate of $89 to $93 million.

Apple has asked its suppliers to cut iPhone XR, XS, and XS Max production by 10 percent for the next three months and has implemented its own reduction in hiring for certain divisions amid the slump.

The company is attempting to boost iPhone sales by dropping prices in China and offering increased trade-in values in the U.S. and other countries.

Tag: TSMC

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iPhone Suppliers TSMC and Foxconn Report Strong November Revenue

Two of Apple's largest suppliers have reported healthy jumps in monthly revenue, suggesting fears of weak iPhone demand may be overblown (via Bloomberg).

Asian firms TSMC and Foxconn (Hon Hai) both posted a 5.6 percent rise in November sales, reversing a recent trend of Apple suppliers reducing production or revenue outlooks to reflect lowering demand for Apple's smartphones.


Foxconn posted NT$601.4 billion ($19.5 billion) in revenue, a record for the month of November, which puts the iPhone assembler on track for its fastest pace of annual growth in years.

TSMC, maker of Apple's system-on-chips like the A12 processor, reported revenue of $3.1 billion, a lower figure than the previous month but still considered strong overall. Executives at the chipmaker have said they expect demand for premium devices to help offset lethargy in the crypto-mining market, which it has heavily invested in.

Apple accounts for close to half of main iPhone-assembler Hon Hai's revenue and about a fifth of TSMC's, according to data compiled by Bloomberg.

The figures offer something of a riposte to the narrative that sales of Apple's iPhone XR and XS have been weaker than expected. For example, last week it was reported that Apple moved marketing staff off other projects to focus on bolstering sales of the latest iPhone lineup in late October.

Apple's next earnings call is in January, when investors will get an idea of how the company did over the holiday season, although Apple recently stopped reporting real unit numbers for its major product categories, so investors will have to rely on revenue and gross margin figures alone to assess performance.

Related Roundups: iPhone XS, iPhone XR
Tags: TSMC, Foxconn

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TSMC Expected to Remain Exclusive Supplier of ‘A13’ Chip Orders for 2019 iPhones

Taiwanese manufacturer TSMC will likely remain Apple's contract chipmaker next year, as the exclusive supplier of "A13" chips for 2019 iPhones, according to industry analysts cited in a report by the EE Times.

"As long as TSMC continues to offer something new at leading-edge every year and continues to execute well on yield, I could see Apple remaining sole source on foundry at TSMC for years to come," Arete Research analyst Brett Simpson said in an interview with EE Times.
TSMC has been Apple's exclusive supplier of A-series chips since 2016, fulfilling all orders for the A10 Fusion chip in the iPhone 7 and iPhone 7 Plus, and the A11 Bionic chip in the iPhone 8, iPhone 8 Plus, and iPhone X. Multiple reports indicate TSMC will also be the exclusive supplier of the "A12" chip in 2018 iPhones.

TSMC's packaging offerings are widely considered to be superior to that of other chipmakers, including Samsung and Intel, so it won't be surprising if that exclusivity continues with the "A13" chip in 2019.

TSMC has been gradually shrinking the size of its dies over the years as it continues to refine its manufacturing process: A10 Fusion is 16nm, A11 Bionic is 10nm, and this year's "A12" is expected to be a 7nm chip. The "A13" will likely be a 7nm+ chip with extreme ultraviolet lithography (EUV), with volume production expected to begin in the second quarter of 2019, in time for a fall iPhone launch next year.

Beyond that, TSMC recently confirmed that it plans to invest $25 billion towards volume production of 5nm chips by 2020, so there's a good chance that Apple will rely on the Taiwanese chipmaker for the foreseeable future.

TSMC's favor with Apple comes at the expense of Samsung, which was the exclusive manufacturer of iPhone processors for many years, starting with the ARM11 chip in the original iPhone through to the A8 chip in the iPhone 6 and iPhone 6 Plus. In 2015, Apple dual sourced A9 chips from both Samsung and TSMC.

Samsung isn't backing down easily, however, as DigiTimes last month reported that the South Korean company is developing its own InFO packaging technology. Samsung claims to have outpaced TSMC in kicking off official production of 7nm+ with EUV, seeking to win back orders from Apple in 2019.

As far as how this all impacts customers, Apple's industry-leading mobile chip designs and TSMC's continued packaging advancements are beneficial for the performance, battery life, and thermal management of future iPhones.

Tag: TSMC

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Apple Supplier TSMC Recovering From ‘Debilitating’ Computer Virus

Apple supplier Taiwan Semiconductor Manufacturing Company is in recovery from a "debilitating" computer virus that hit many of its fabrication tools this past Friday evening. The company says that 80 percent of the affected tools have been restored, but it's now on a path to warn its customers -- potentially including Apple -- of delayed shipments and reduced revenue due to the virus (via Bloomberg).


TSMC builds chips for Apple's iPhone, and in late July a report from DigiTimes stated that the supplier had begun commercial production of chips manufactured using its advanced 7-nanometer process, including Apple's A12 processor for the 2018 iPhones. Now TSMC says many of its customers can expect shipment delays, although it didn't specify which customers would be affected.

The supplier says that "no confidential information" was compromised during the virus attack and as of Sunday most of its customers had been notified. TSMC believes the virus came from a "misoperation" during the software installation process for a new tool that then spread through its computer network, and one analyst thinks "all of TSMC's 12-inch wafer fabrication plants" were infected.
Mark Li, an analyst at Sanford C. Bernstein, said he thinks all of TSMC’s 12-inch wafer fabrication plants had been infected and that many customers had been affected, though the impact will be “very limited” because the company can make up for the losses during the busiest holiday quarter. TSMC makes Apple chips in its 12-inch fabrication plants.

“Long-term, TSMC’s trustworthy image is somewhat tainted but it is hard to quantify the effect now,” Li wrote in a research note Monday.
Although it's unclear how the virus will end up affecting Apple and the trio of iPhones expected to be revealed next month, Apple is TSMC's largest customer and is said to account for more than 21 percent of TSMC's revenue. Apple chose TSMC to remain the exclusive supplier of the upcoming A12 processor for the new iPhones, following rumors from last year that suggested Samsung could be returning to iPhone chip production in 2018.

Despite the fear over chip shipment delays, Apple is likely to have plans in place for any potential supply chain delays, as Bloomberg points out:
While TSMC has not indicated which customers could be affected, such a virus could potentially slow Apple’s output of new devices, cutting into the number of units sold.

Apple does prepare for last minute supply-chain hiccups like the one facing TSMC and could work through any potential problems. An Apple spokesperson didn’t immediately respond to a request for comment on Sunday.

“If the most advanced 7nm process products suffer a major impact, then concern could arise over a potential launch delay for next-gen iPhones,” SMBC Nikko analysts wrote on Monday.
Apple is expected to announce three iPhone models at an event in September: two OLED models measuring in at 5.8 and 6.5 inches and a 6.1-inch lower-cost LCD model. All three iPhones released in 2018 will support Face ID and edge-to-edge displays, with designs similar to last year's tenth-anniversary iPhone X. According to the latest supply chain analysis (which came prior to TSMC's virus attack), the OLED iPhones were predicted to have a typical September launch window while the LCD model could "possibly" be delayed to October.

Related Roundup: 2018 iPhones
Tag: TSMC

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TSMC Ramps Up Production of 7nm Chips Ahead of 2018 iPhones, Invests $25 Billion to Move to 5nm by 2020

Apple supplier Taiwan Semiconductor Manufacturing Company has begun commercial production of chips manufactured using its advanced 7-nanometer process (via DigiTimes). One of the major customers for chips built with the technology will be Apple and the A12 processor, which is expected to be found in all three upcoming 2018 iPhones.

The announcement comes from newly appointed TSMC CEO C.C. Wei, who spoke during the company's technology symposium in Taiwan yesterday in hopes of dismissing recent speculation that TSMC's 7nm production was facing a "slower-than-expected" yield rate. Wei didn't provide specific orders and customers for the 7nm chip output, but indicated the ramp up will boost TSMC's overall production capacity from 10.5 million wafers in 2017 to 12 million in 2018.

Renderings of the 2018 iPhones

The chips built using the 7nm process technology are destined for AI, GPU, cryptocurrency, and 5G applications -- totaling 50 chip designs by the end of 2018. For iPhones, the new 7nm process will pave the way for the type of performance improvements customers expect in new iPhones every year.
Orders for Apple's custom A12 processor for use in the upcoming iPhones will play a major driver of TSMC's 7nm chip production growth in 2018, according to market sources. The foundry has secured 7nm chip orders from about 20 customers including AMD, Bitmain, Nvidia and Qualcomm. The majority of the orders will be carried out in the first half of 2019, the sources said.
At the technology symposium, Wei also said that TSMC is scheduled to move a new 5nm node technology to mass production towards the end of 2019 or early 2020, with plans to invest $25 billion into the technology.

In January, DigiTimes reported that Apple selected TSMC to remain the exclusive supplier of the upcoming A12 processor for its 2018 iPhones, following rumors from last summer that Samsung could be returning to iPhone chip production this year. TSMC is the exclusive supplier of the A11 Bionic processor found in the iPhone 8, 8 Plus, and X, as well as the sole supplier of the A10 Fusion processor in the iPhone 7 and 7 Plus.

According to a DigiTimes report last year, TSMC's integrated fan-out wafer-level packaging technology -- which the supplier uses in its 7nm FinFET chip fabrication -- is largely superior to any progress made by Samsung in the same field, which eventually led to Apple's decision to stick with one supplier for all of its processors again this year.

Apple's decision to keep TSMC as the sole A-series chip manufacturer in 2018 will mark the third year in a row that the supplier created iPhone chips alone, following the A10 in 2016 and the A11 Bionic in 2017. The last time Apple dual sourced chips was in 2015, when both Samsung and TSMC supplied the A9 chip in the iPhone 6s and iPhone 6s Plus, which frustrated some users when TSMC's technology was discovered to boast slightly better battery life.

Related Roundup: 2018 iPhones
Tag: TSMC

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Patent Applications Reveal Apple’s Research Into 3D Chip Packaging

Apple's persistent quest for better performance, longer battery life, and slimmer form factors appears to be driving its research into advanced chip packaging technologies. So-called "2.5D" and "3D" packaging methods stand to offer significant gains in all of these areas by increasing memory bandwidth, reducing power consumption, and freeing up space for higher-capacity batteries.

Apple has been an aggressive adopter of new device packaging methods, mostly thanks to integrated fan-out (InFO) innovations provided by foundry partner TSMC. TSMC's success has spurred it into further developing and diversifying its packaging offerings, and TSMC has emerged as an industry leader in packaging techniques.


While versions of TSMC's InFO packaging have brought performance improvements to Apple devices, such as better thermal management and improved package height, it has largely not been a direct enabler of improved electrical performance. This is set to change with future packaging techniques and is already seen in some products that utilize interposers for higher density interconnects to on-package memory, such as High Bandwidth Memory (HBM).

The primary memory candidate for inclusion in such a package would be conforming to the Wide I/O set of standards described by JEDEC, and mentioned by name in several of the patents. This memory improves on LPDDR4 by increasing the number of channels and reducing the transfer speed per channel, thus increasing the overall bandwidth but lowering the energy required per bit.

Interposers do, however, pose several issues for mobile devices. Significantly, they introduce another vertical element to the package, increasing total height. Interposers must also be fabricated on silicon wafers just like active ICs, with their dimensions driven by the footprint of all devices that need to be included in the package. These solutions are typically termed as "2.5D" due to some components being placed laterally with respect to one another rather a true stacking of chips.

Rather than adopt interposers for its products as a next step in advanced packaging, the direction of Apple's focus, according to several patent applications [1][2][3][4], appears to be on true "3D" techniques, with logic die such as memory being placed directly on top of an active SoC. Additionally, a patent application from TSMC seems to suggest a level of coordination between Apple and TSMC in these efforts.

3D stacking process flow

The process has similarities to the existing InFO techniques in that they both involve a redistribution layer (RDL) where contacts on a logic die are routed inside a molding compound with the help of vias directly in the molding compound. Where the 3D process diverts from this is that there is now RDL content on both sides of the die, necessitating the use of through-silicon vias (TSV) directly in the logic die so that interconnections can be made with the top of the die. A key feature of these RDL layers is that interconnect pitches finer than available substrate or interposer types is possible.

Subsequent dies could then be attached to the molding compound, mating with the vias and RDL placed in the previous step. This step could be done multiple times, provided each stacked component has TSVs for the next level of integration, and this is already seen in HBM, which allows for the stacking of up to eight DRAM dies.

Side view of memory die (110) attached to SoC (150) in 3D package

Still, this approach has many technical challenges that have prevented its commercialization. TSVs are expensive to implement and are a serious yield detractor to ICs. Electrical isolation from nearby components' radiated energy can also be a concern, particularly when integrating RF and analog components in a package with other components that would have been separated by space and EMI shielding before. Apple describes techniques to incorporate shielding directly in the package to mitigate this.

Package with integrated EMI shield

This approach also presents thermal challenges since active dies become so closely coupled in mediums that have poor thermal conductivity and shared thermal paths. These concerns extend not only to normal device usage, but also the package integration and any solder reflow steps. Thermal stresses can induce warpage of the packaging components due to differing coefficients of thermal expansion (CTE) amongst the materials utilized in the package. This warpage can lead to broken or separated contacts, resulting in device failure.

The use of a carrier substrate in the process flow mitigates some of the thermal concerns. The direct integration of heatsinks into device packaging is also addressed at various levels of the package assembly, such that higher dissipating die, such as a SoC featuring CPU and GPU cores, could be placed on the bottom of the stack or at a higher level of integration, providing stackup flexibility not seen in previous PoP arrangements.

Package with integrated heatsink component (310)
Embodiments may be applied in applications such as, and not limited to, low power and/or high I/O width memory architecture. Embodiments can enable a short double data rate (DDR) channel to neighboring function units (e.g. SOC, chipsets, etc.) by using RDL and direct chip attach. Embodiments may be particularly applicable for mobile applications that require low power DDR at target performance including high speed and I/O width.
The benefits of the methods described are many. The use of higher bandwidth memory will yield performance improvements. The flexibility of component placement shortens the distance between connected active and passive devices, either lowering the energy required to communicate between them, or reducing parasitic effects that can cause unwanted power loss or dynamic performance degradation. The most notable tasks that stand to benefit are gaming and image processing tasks, which often require large amounts of bandwidth over short time intervals.

Apple Watch Implications


These enhancements would be applicable to all of Apple's mobile devices, but multiple patent applications specifically mention methods of multiple components married together in a System in Package (SiP), as seen in the current Apple Watch. The methods described below are an enhancement on the existing SiP solutions found in Apple Watch in that they introduce true 3D stacking elements enabled by both TSV and Through Oxide Vias (TOV).

Array of TOVs for connecting stacked die to package pins
In one aspect, embodiments describe system on chip (SoC) die portioning and/or die splitting within an SiP structure (e.g. 3D memory package) in which IP cores such as CPU, GPU, IO, DRAM, SRAM, cache, ESD, power management, and integrated passives may be freely segregated throughout the package, while also mitigating total z-height of the package.
Additionally, the patent describes TSV and TOV pitch in explicit detail, suggesting that keeping package heights down allows them to create very small width vias, with the TOV forming interconnect rows at sizes smaller than even the TSVs. The effect of TSVs stressing active parts of the die, including hurting transistor performance, is also discussed, and the reduced pitches help to mitigate this.

Active die keepout zones around TSVs

Inclusion of RF transceivers and active devices on substrate types not currently used in Apple mobile devices are covered, indicating all types of active and passive components found in Apple Watch products could be housed in the SiP proposed.

Bottom level view of an SiP with stacked heterogenous die interconnected with TSV and TOV

Timeline


Packages featuring 2.5D and 3D connected components have been in consumer devices for several years, but most of the methods described above have yet to debut in mobile devices. The steps described are set to increase manufacturing complexity, and cost and throughput will likely suffer as a result.

Due to cost and yield concerns, a primary candidate for first inclusion of these methods would be a high-margin, low-quantity device. While the iPhone is the highest margin of Apple's mobile products, it is also the largest volume category, with a huge initial demand for each generation. The iPad Pro is a good candidate because of its low volume nature and its classification as a high-performance device. The inclusion of 120Hz refresh rate is something that will benefit from increased memory bandwidth, specifically.

The focus of many of these patents seems to be specifically on SiP methods seen in Apple Watch internals. The Apple Watch is a lower-volume device, and it stands to benefit because its internals are extremely sensitive to package size given the importance of its form factor and battery size. It seems reasonable to expect some of the methods described to be incorporated as soon as the next revision of the Apple Watch, and more progressively in future revisions.

Related Roundups: Apple Watch, watchOS 4, watchOS 5
Tag: TSMC
Buyer's Guide: Apple Watch (Neutral)

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TSMC Details Technology Roadmap With Multiple Offerings to Benefit Future Apple Devices

As part of its recent Q1 earnings call, TSMC announced that its 7-nanometer FinFET process node has entered into high volume manufacturing (HVM), meaning we could see consumer devices featuring the process as soon as the second half of this year.

Previous reports indicated that TSMC is expected to have sole production responsibility for Apple's upcoming A12 chip and its variants expected to debut in new iPhone and iPad products starting this fall. The 7nm node (referred to as CLN7FF, 7FF, or simply N7) is expected to have an approximate 40 percent power and area benefit over TSMC's 10nm FinFET process, utilized in Apple's A11 processors.

Additionally, as reported by EETimes, TSMC has offered insight into its technology roadmap, both for its silicon processes and for its device packaging technologies. TSMC is believed to have wrested sole ownership of production for Apple's processors away from the dual-sourcing arrangement with Samsung due to its advancements in wafer-level packaging. (What also went largely unnoticed at the time was TSMC's introduction of land-side capacitors attached directly to the substrate.)

Building on the packaging leadership established with its InFO packaging offerings, TSMC has now announced six new packaging types aimed at a variety of devices and applications.


The InFO technique is getting four cousins. Info-MS, for memory substrate, packs an SoC and HBM on a 1x reticle substrate with a 2 x 2-micron redistribution layer and will be qualified in September.

InFO-oS has a backside RDL pitch better matched to DRAM and is ready now. A multi-stacking option called MUST puts one or two chips on top of another larger one linked through an interposer at the base of the stack.

Finally, InFO-AIP stands for antenna-in-package, sporting a 10% smaller form factor and 40% higher gain. It targets designs such as front-end modules for 5G basebands.

But that’s not all. TSMC introduced two wholly new packaging options. A wafer-on-wafer pack (WoW) directly bonds up to three dice. It was released last week, but users need to ensure that their EDA flows support the bonding technique. It will get EMI support in June.

Finally, the foundry roughly described something that it called system-on-integrated-chips (SoICs) using less than 10-micron interconnects to link two dice, but details are still sketchy for the technique to be released sometime next year. It targets apps from mobile to high-performance computing and can connect dice made in different nodes, suggesting it may be a form of system-in-package.
The announcement of these packaging technologies is important because they will enable a variety of different package and interconnect structures for Apple's SoCs, with the immediate benefit being novel interfaces to in-package memory. While InFO offers height, performance and thermal advantages for Apple, they still must interconnect to the RAM seated on top of the application processor through the use of wire bonds in a package-on-package configuration.

This interface presents thermal challenges and limits the width and speed of the memory bus interface due to the type of interconnects. The IC industry has seen quite a bit of effort into novel memory technologies such as High Bandwidth Memory (HBM), but this technology has largely been relegated to graphics processors aimed at scientific, research, and extreme enthusiast use due to the high cost and low yield associated with the silicon interposers that enable the chip-to-memory connections. The fact that TSMC has unveiled a variant of InFO directly aimed at this solution bodes well for its increased adoption in the industry in a variety of products.

The InFO-oS process is of much more near-term interest for mobile device makers such as Apple, where the memory bus widths would be much lower, but the per-pin bandwidth is much higher, as seen in LPDDR4. According to a TSMC report, the "oS" portion this technology refers to on-substrate, where die-partitioning would take place.

This would seem to allow for a 2.5D solution where the memory die is placed alongside the processor die as opposed to suspended above via a mold compound as seen in the original InFO-WLP packaging, enabling the higher interconnect density. However, the retention of a redistribution layer means a mold compound must still be in play, so a more thorough technical disclosure could help eliminate some of the ambiguity with this naming convention. While this would eliminate die-stacking, it would increase the total footprint of the packaged solution, which would still be a concern in a size-constrained mobile package.

TSMC InFO variants

While Apple could eventually move to an HBM solution, which affords much greater memory bandwidth at lower power levels, the wafer-on-wafer (WoW) announcement is a genuine step towards true 3D integrated circuits, where eventually dies would be stacked directly on top of each other and interconnected through vias placed directly in the IC die.

The innovation for TSMC here would be in exactly how it packages these dies together, and what the interfaces look like as well as what type of redistribution layers (RDLs) they offer. While not directly applicable to Apple's line of processors, the InFO-AIP is also an important development, as radio frequency (RF) front-ends stand to take on another order of complexity with their adoption of much wider frequency bandwidths needed for 5G standards.

Beyond the 7nm node, TSMC also shared its outlook for the foundry's successive nodes, 7nm+ and 5nm. 7nm+ will be TSMC's first node to feature extreme ultraviolet (EUV) lithography, which stands to simplify the mask process by eliminating the need for multiple patterning in many areas to define smaller features.

Following 7nm+ will be 5nm, which would enter risk production late next year if current timelines hold, meaning volume production would occur sometime in 2020, though likely too late for a fall 2020 product launch, even with the most optimistic timelines. Though EUV has been long-awaited and will solve many problems in the industry, it brings a host of its own issues and will not bring huge performance jumps in successive nodes, nor will it grant smoother node transitions, as 5nm already presents its own EUV challenges.
The node delivers 35% more speed or uses 65% less power and sports a 3x gain in routed gate density. By contrast, the N7+ node with EUV will only deliver 20% more density, 10% less power, and apparently no speed gains — and those advances require use of new standard cells.
Still, the above news is encouraging, as Apple should be able to enjoy the benefits of a new technology node for at least two out of the next three years. This will offer a boost as its processor architecture gains slow down, and the advent of new packaging techniques will allow Apple to overcome bandwidth and thermal constraints in ways that were simply not possible before.

TSMC has also offered hope for the future, painting the picture beyond 5nm in broad strokes with plans for newer transistor topologies such as silicon nanowires, and moving beyond silicon as the prime semiconducting medium to materials that ultimately offer higher carrier (electrons and holes) mobility.

TSMC also detailed ways to improve the conductivity and reduce the parasitics associated with the interconnects present in the silicon die. Ultimately, these interconnects often dictate how quickly transistors can switch due to the effective line load on them, and that is a concern all the way from the die to the package and on to the PCB. TSMC seems to be diligently pursuing a variety of solutions for its customers on two of those fronts, and its packaging solutions are bringing more and more of those PCB components straight into the device package to combat the third element.

Tags: TSMC, A12

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Apple A12 and Snapdragon 700 Chip Production May Lead TSMC to Earn Record Profits in 2018 After All

Last week, Apple supplier TSMC saw its shares decline around nine percent after it cut its full-year revenue growth target to 10 percent, compared to its previous 10-15 percent estimate. The manufacturer blamed the cut on lower-than-expected smartphone demand and growing uncertainty in the cryptocurrency mining market.


Apple's stock also declined around four percent on Friday, as many analysts equated the slowing smartphone demand with poor or declining sales of the iPhone X, which has an A11 Bionic chip fabricated by TSMC, in the second quarter.

Now, a report from DigiTimes suggests that TSMC may post better-than-projected revenues and profits in 2018 after all, as it gradually ramps up volume production of so-called A12 chips for Apple's next-generation iPhone lineup. The wafers are expected to be manufactured based on TSMC's advanced 7nm process.
The sources said that TSMC will see its revenue ratio for advanced 7nm process hit a high of 20 percent in 2018, and may therefore post better-than-projected revenues and profits for the second half of the year and register an annual revenue growth of over 10 percent.
TSMC may also benefit from Qualcomm's decision to roll out its new Snapdragon 700 series processors in May, ahead of schedule, according to the report. Qualcomm has allegedly grabbed significant orders from non-Apple smartphone vendors and will have TSMC fabricate the chips in the second half of the year.

The report is questionable given that TSMC presumably factored in production of A12 chips into its revenue guidance last week, but the better-than-projected revenues could rest more on the Qualcomm portion of the news.

How much money TSMC makes is a data point that Apple analysts often attempt to interpret in order to gauge iPhone sales. A constant flow of reports have claimed iPhone X sales have significantly declined following the device's late 2017 launch quarter, but Apple has yet to disclose any official figures.

Apple will report its second quarter earnings results on Tuesday, May 1, including how many iPhones it sold during the January-March period, but it doesn't provide a model-by-model breakdown of sales. Apple reported record-breaking revenue of $88.3 billion and 77.3 million iPhone sales in the first quarter.


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