TSMC Details Technology Roadmap With Multiple Offerings to Benefit Future Apple Devices

As part of its recent Q1 earnings call, TSMC announced that its 7-nanometer FinFET process node has entered into high volume manufacturing (HVM), meaning we could see consumer devices featuring the process as soon as the second half of this year.

Previous reports indicated that TSMC is expected to have sole production responsibility for Apple's upcoming A12 chip and its variants expected to debut in new iPhone and iPad products starting this fall. The 7nm node (referred to as CLN7FF, 7FF, or simply N7) is expected to have an approximate 40 percent power and area benefit over TSMC's 10nm FinFET process, utilized in Apple's A11 processors.

Additionally, as reported by EETimes, TSMC has offered insight into its technology roadmap, both for its silicon processes and for its device packaging technologies. TSMC is believed to have wrested sole ownership of production for Apple's processors away from the dual-sourcing arrangement with Samsung due to its advancements in wafer-level packaging. (What also went largely unnoticed at the time was TSMC's introduction of land-side capacitors attached directly to the substrate.)

Building on the packaging leadership established with its InFO packaging offerings, TSMC has now announced six new packaging types aimed at a variety of devices and applications.


The InFO technique is getting four cousins. Info-MS, for memory substrate, packs an SoC and HBM on a 1x reticle substrate with a 2 x 2-micron redistribution layer and will be qualified in September.

InFO-oS has a backside RDL pitch better matched to DRAM and is ready now. A multi-stacking option called MUST puts one or two chips on top of another larger one linked through an interposer at the base of the stack.

Finally, InFO-AIP stands for antenna-in-package, sporting a 10% smaller form factor and 40% higher gain. It targets designs such as front-end modules for 5G basebands.

But that’s not all. TSMC introduced two wholly new packaging options. A wafer-on-wafer pack (WoW) directly bonds up to three dice. It was released last week, but users need to ensure that their EDA flows support the bonding technique. It will get EMI support in June.

Finally, the foundry roughly described something that it called system-on-integrated-chips (SoICs) using less than 10-micron interconnects to link two dice, but details are still sketchy for the technique to be released sometime next year. It targets apps from mobile to high-performance computing and can connect dice made in different nodes, suggesting it may be a form of system-in-package.
The announcement of these packaging technologies is important because they will enable a variety of different package and interconnect structures for Apple's SoCs, with the immediate benefit being novel interfaces to in-package memory. While InFO offers height, performance and thermal advantages for Apple, they still must interconnect to the RAM seated on top of the application processor through the use of wire bonds in a package-on-package configuration.

This interface presents thermal challenges and limits the width and speed of the memory bus interface due to the type of interconnects. The IC industry has seen quite a bit of effort into novel memory technologies such as High Bandwidth Memory (HBM), but this technology has largely been relegated to graphics processors aimed at scientific, research, and extreme enthusiast use due to the high cost and low yield associated with the silicon interposers that enable the chip-to-memory connections. The fact that TSMC has unveiled a variant of InFO directly aimed at this solution bodes well for its increased adoption in the industry in a variety of products.

The InFO-oS process is of much more near-term interest for mobile device makers such as Apple, where the memory bus widths would be much lower, but the per-pin bandwidth is much higher, as seen in LPDDR4. According to a TSMC report, the "oS" portion this technology refers to on-substrate, where die-partitioning would take place.

This would seem to allow for a 2.5D solution where the memory die is placed alongside the processor die as opposed to suspended above via a mold compound as seen in the original InFO-WLP packaging, enabling the higher interconnect density. However, the retention of a redistribution layer means a mold compound must still be in play, so a more thorough technical disclosure could help eliminate some of the ambiguity with this naming convention. While this would eliminate die-stacking, it would increase the total footprint of the packaged solution, which would still be a concern in a size-constrained mobile package.

TSMC InFO variants

While Apple could eventually move to an HBM solution, which affords much greater memory bandwidth at lower power levels, the wafer-on-wafer (WoW) announcement is a genuine step towards true 3D integrated circuits, where eventually dies would be stacked directly on top of each other and interconnected through vias placed directly in the IC die.

The innovation for TSMC here would be in exactly how it packages these dies together, and what the interfaces look like as well as what type of redistribution layers (RDLs) they offer. While not directly applicable to Apple's line of processors, the InFO-AIP is also an important development, as radio frequency (RF) front-ends stand to take on another order of complexity with their adoption of much wider frequency bandwidths needed for 5G standards.

Beyond the 7nm node, TSMC also shared its outlook for the foundry's successive nodes, 7nm+ and 5nm. 7nm+ will be TSMC's first node to feature extreme ultraviolet (EUV) lithography, which stands to simplify the mask process by eliminating the need for multiple patterning in many areas to define smaller features.

Following 7nm+ will be 5nm, which would enter risk production late next year if current timelines hold, meaning volume production would occur sometime in 2020, though likely too late for a fall 2020 product launch, even with the most optimistic timelines. Though EUV has been long-awaited and will solve many problems in the industry, it brings a host of its own issues and will not bring huge performance jumps in successive nodes, nor will it grant smoother node transitions, as 5nm already presents its own EUV challenges.
The node delivers 35% more speed or uses 65% less power and sports a 3x gain in routed gate density. By contrast, the N7+ node with EUV will only deliver 20% more density, 10% less power, and apparently no speed gains — and those advances require use of new standard cells.
Still, the above news is encouraging, as Apple should be able to enjoy the benefits of a new technology node for at least two out of the next three years. This will offer a boost as its processor architecture gains slow down, and the advent of new packaging techniques will allow Apple to overcome bandwidth and thermal constraints in ways that were simply not possible before.

TSMC has also offered hope for the future, painting the picture beyond 5nm in broad strokes with plans for newer transistor topologies such as silicon nanowires, and moving beyond silicon as the prime semiconducting medium to materials that ultimately offer higher carrier (electrons and holes) mobility.

TSMC also detailed ways to improve the conductivity and reduce the parasitics associated with the interconnects present in the silicon die. Ultimately, these interconnects often dictate how quickly transistors can switch due to the effective line load on them, and that is a concern all the way from the die to the package and on to the PCB. TSMC seems to be diligently pursuing a variety of solutions for its customers on two of those fronts, and its packaging solutions are bringing more and more of those PCB components straight into the device package to combat the third element.

Tags: TSMC, A12

Discuss this article in our forums

Apple A12 and Snapdragon 700 Chip Production May Lead TSMC to Earn Record Profits in 2018 After All

Last week, Apple supplier TSMC saw its shares decline around nine percent after it cut its full-year revenue growth target to 10 percent, compared to its previous 10-15 percent estimate. The manufacturer blamed the cut on lower-than-expected smartphone demand and growing uncertainty in the cryptocurrency mining market.


Apple's stock also declined around four percent on Friday, as many analysts equated the slowing smartphone demand with poor or declining sales of the iPhone X, which has an A11 Bionic chip fabricated by TSMC, in the second quarter.

Now, a report from DigiTimes suggests that TSMC may post better-than-projected revenues and profits in 2018 after all, as it gradually ramps up volume production of so-called A12 chips for Apple's next-generation iPhone lineup. The wafers are expected to be manufactured based on TSMC's advanced 7nm process.
The sources said that TSMC will see its revenue ratio for advanced 7nm process hit a high of 20 percent in 2018, and may therefore post better-than-projected revenues and profits for the second half of the year and register an annual revenue growth of over 10 percent.
TSMC may also benefit from Qualcomm's decision to roll out its new Snapdragon 700 series processors in May, ahead of schedule, according to the report. Qualcomm has allegedly grabbed significant orders from non-Apple smartphone vendors and will have TSMC fabricate the chips in the second half of the year.

The report is questionable given that TSMC presumably factored in production of A12 chips into its revenue guidance last week, but the better-than-projected revenues could rest more on the Qualcomm portion of the news.

How much money TSMC makes is a data point that Apple analysts often attempt to interpret in order to gauge iPhone sales. A constant flow of reports have claimed iPhone X sales have significantly declined following the device's late 2017 launch quarter, but Apple has yet to disclose any official figures.

Apple will report its second quarter earnings results on Tuesday, May 1, including how many iPhones it sold during the January-March period, but it doesn't provide a model-by-model breakdown of sales. Apple reported record-breaking revenue of $88.3 billion and 77.3 million iPhone sales in the first quarter.


Discuss this article in our forums

TSMC is Reportedly Exclusive Supplier of A12 Processors in 2018 iPhones

Apple has reportedly selected Taiwanese manufacturing company TSMC to remain its exclusive supplier of so-called "A12" processors for a trio of new iPhone models expected to launch in the second half of 2018, according to DigiTimes.


The report, citing unnamed sources within Apple's supply chain, claims the A12 chip will be manufactured based on a 7nm process and incorporate extreme ultraviolet technology, allowing for more transistors to be packed into a smaller wafer, and paving the way for continued performance improvements in the next iPhones.

TSMC is already the exclusive supplier of A11 Bionic chips for the iPhone 8, iPhone 8 Plus, and iPhone X, and it was also said to be the sole manufacturer of A10 Fusion chips for the iPhone 7 and iPhone 7 Plus.

If the report is accurate, it would be a loss for Samsung, which has been attempting to win back orders from Apple for around two years. Both Samsung and TSMC supplied Apple with A9 chips for the iPhone 6s, iPhone 6s Plus, and iPhone SE, but Apple has relied upon TSMC as its sole supplier for newer devices.

The Korea Herald last July reported that Samsung had secured a deal to supply some of the A12 chips for new iPhones in 2018, but two days later, DigiTimes reported that TSMC was still likely to obtain all of the next-generation A-series chip orders for Apple's upcoming 2018 series of iPhones.

TSMC's in-house InFO wafer-level packaging is said to make its 7nm FinFET technology more competitive than Samsung's. Our own Chris Jenkins provided an in-depth technical look at this package process last September.

Related Roundup: iPhone X
Buyer's Guide: iPhone X (Buy Now)

Discuss this article in our forums

Apple’s Chip Partner TSMC Shares Details on 7nm Node and Advanced InFO Package Process for 2018

At the Open Innovation Platform Ecosystem Forum in Santa Clara on Wednesday, chip foundry TSMC provided an update (via EE Times) on the progress of its forthcoming technology nodes, several of which would be candidates for upcoming Apple chips. Most notably, the company's first 7-nanometer process node has already had several tape-outs (finalized designs) and expects to reach volume capacity in 2018.

TSMC's 10 nm node, which first showed up in Apple's A10X chip in the iPad Pro, followed by the A11, has been fraught with issues (paid link) such as low chip yield and performance short of initial expectations. TSMC looks to change its fortune with the new 7 nm node, which would be suitable for the successor to the A11 chip given current timelines.

In addition to the 7 nm node, TSMC also shared information on the follow-up revision to this node, dubbed, N7+. Featuring the long-beleaguered Extreme Ultraviolet Lithography (EUV), the revision would promise 20 percent better density, around 10 percent higher speeds, or 15 percent lower power with other factors held constant.

While EUV has faced delays for over a decade at this point, it seems to finally be coming to fruition, and a 2019 volume availability update would allow Apple to update its chip process in subsequent years yet again. Apple had previously updated process nodes with every iPhone since the transition to 3GS before being forced to use TSMC's 16 nm node in consecutive years with the A9 and A10. Moving forward, that annual cadence is again in jeopardy as chip foundries deal with the realities of physics and minimum transistor geometry sizes.

TSMC also unveiled some low power and low leakage processes that are suitable for Apple's other custom designs, such as its line of wireless chips like the W1 and successor W2. TSMC is targeting availability next year of a 22 nm ultra low leakage node, which is suitable for analog and RF designs such as cellular basebands or Wi-Fi chips.

This will ultimately help Apple further lower power consumption on the Apple Watch and headphones featuring the W line of wireless chips. It is also likely to be adopted by Qualcomm for its line of modem products. The W1 and W2 manufacturing processes are not currently publicly known, but it is likely that one of TSMC's RF-focused processes powers the Apple chips.

Finally, TSMC announced a revision of its integrated fan-out packaging process (InFO) that is targeted at integrating high bandwidth memory (HBM) into the assembly, dubbed InFO-MS. HBM has generated a lot of interest from applications where very high sustained memory bandwidths are desired, such as consumer graphics cards.

HBM and similar standards such as Wide I/O promise not only to improve memory bandwidth, but also improve power consumption for a given bandwidth, making it a suitable evolution for mobile SoC designs. This type of memory interface has yet to appear in a mobile design, though it should be considered a near-term eventuality. Despite advances in mobile memory, it still lags behind desktop and laptop systems in total bandwidth, which can be important in some tasks such as graphics rendering.

Tags: TSMC, W1, A12, W2

Discuss this article in our forums